1. Technical Field
The present invention relates to a semiconductor device and a power source control method, and in particular relates to a semiconductor device and a power source control method well-suited to performing reliable startup control, for example, in a power source circuit provided in a Large Scale Integration (LSI).
2. Related Art
Semiconductor devices such as LSIs are provided with, for example, a power source circuit that generates a power source voltage VDDL that is lower than an externally input power source voltage VDD, and a control circuit (also referred to below as an LSI control circuit) that uses the voltage VDDL generated by the power source circuit to control respective circuit operations within the semiconductor device. The LSI control circuit enables a reduction in power consumption due to controlling the respective circuit operations using the voltage VDDL that is lower than the voltage VDD.
Semiconductor devices configured in this manner generally include a power down mode in which circuits are paused under specific conditions, with the aim of further reducing power consumption. For example, control is made such that when there is a drop in the battery voltage of a secondary battery that is the power source of the electronic circuits mounted on the semiconductor device, the power source circuit transitions to the power down mode, output of the power source voltage is shut off, and current consumption of the electronic circuits is suppressed to a minimum until the voltage of the rechargeable battery has recovered. Then, once the battery voltage has recovered due to, for example, recharging the rechargeable battery, control is made to restore the power source circuit from the power down mode and allow supply of the power source voltage VDDL to return the electronic circuits to a normal operating state.
However, when, for example as described in Japanese Patent Application Laid-Open (JP-A) No. 2011-211512, output of an internal power source voltage is stopped and started during transition to a power down mode, or recovery from the power down mode, various faults can occur in which unstable operation of the electrical circuit, different from normal operation, occurs during this switching.
JP-A No. 2011-211512 describes technology in which output of an abnormal signal from a level shifter occurring during transition to the power down mode is eliminated by interrupting an internal power source voltage using a short circuit control signal of a startup signal for controlling the power down mode imparted with a specific delay.
The present invention addresses the point in related technology, including that of JP-A No. 2011-211512, of being unable to avoid faults in which the power source circuit does not start up correctly in configurations in which a power down signal, output from an LSI control circuit that uses the output voltage (VDDL) from the power source circuit as a power source, is input to a power down terminal of the power source circuit.
Namely, in related semiconductor devices provided with a power down mode, the power source circuit itself is provided with a power down function in order to enable external application of the voltage VDDL, and eliminate impact on the power source circuit, when testing characteristics such as, for example, dependency on power source voltage of an LSI control circuit using a voltage VDDL generated by the power source circuit.
Such power source circuits are provided with a terminal (also referred to below as a power down terminal) that is input with an externally input power down signal. The power down signal is output from the LSI control circuit and input to the power down terminal of the power source circuit.
However, there is a risk of the power source circuit starting up incorrectly in such a configuration, in which the power source circuit is provided with a power down function and the power down signal is output from the LSI control circuit that uses the output voltage (VDDL) as the power source and input to the power down terminal of the power source circuit.
For example, when the power source is introduced, the power source circuit does not generate the voltage VDDL (VDDL=0V). When this is the case, the power down signal from the LSI control circuit is normally at a L (low) level that does not cause the power source circuit to power down.
However, the LSI control circuit has a minimum operating voltage. Until the VDDL rises to the minimum operating voltage, the LSI control circuit does not operate normally, and the power down signal from the LSI control circuit becomes indeterminate. There is accordingly a possibility of the power down signal from the LSI control circuit becoming H (high) and causing the power source circuit to power down.
In such power source circuits, technology also exists for causing the power source circuit to power down reliably by inputting a power down signal from the LSI control circuit to the power down terminal of the power source circuit through a level shift circuit that, similarly to the LSI control circuit, uses the output voltage (VDDL) from the power source circuit as a power source.
However, such a level shift circuit also has a minimum operating voltage. Until the voltage VDDL rises to the minimum operating voltage, the level shift circuit does not operate normally. In such configurations, there is moreover no guarantee of the level shift circuit operating normally even when VDDL=0V. For example, when the power source is introduced the power down signal from the level shift circuit is not necessarily L (low) level even when the power down signal from the LSI control circuit is L (low) level, and is sometimes H (high) level. In such cases, the level shift circuit powers down.
Moreover, even when the power down signal from the level shift circuit is at the L (low) level when the power source is introduced, there is a possibility of the power down signal from the level shift circuit becoming H (high) with the subsequent rise in the voltage VDDL, and the power source circuit powering down.